Personal Information
Neha Sharma

Department of Electronics and Communication Engineering, Rama University, Kanpur, Uttar Pradesh, India

Neha Sharma
Educations
From 2007 to 2008, High School , India
From 2009 to 2010, Intermediate , India
From 2011 to 2015, B. Tech. , India
From 2015 to 2017, M. Tech. , India
Work Experiences
From Jan, 2017 to March, 2018, Teaching Associate , Rama University
From April, 2018 to Present, Assistant Professor , Naraina College of Engineering and Technology
Projects
From 09/2010 to 04/2011, Compare the performance evaluation of different modulation techniques with the help of AWGN channel using MATLAB
From 09/2016 to 04/2017, An Advanced Interleaver used for Linear Turbo Equalizer
From 03/2017 to 04/2017, Automatic Power Efficient Smart Street
From 03/2017 to 04/2017, Automatic Water Tank Filler System with Level Indicator
From 03/2017 to 04/2017, Manual Charger
Speciality
Microelectronics & VLSI Design
Electronics & Communication Engineering
Journal Articles
BIT ERROR RATE OF OQPSK VERSUS QPSK
MODIFICATION IN 16:1 MULTIPLEXER BY REVERSIBLE LOGIC
Conference Papers
DESIGN & IMPLEMENTATION OF EFFICIENT TURBO EQUALIZER FOR NOISE REDUCTION
A COMPARATIVE ANALYSIS OF ITERATIVE ALGORITHMS FOR SISO DECODER
A NEW APPROACH FOR EFFICIENT SISO EQUALIZER WITH MODIFIED LEAST MEAN SQUARE ALGORITHM
A COMPARATIVE ANALYSIS OF VARIOUS ADAPTIVE EQUALIZER ALGORITHMS FOR DIFFERENT FREQUENCY SCENARIO
A COMPARATIVE ANALYSIS BETWEEN PWM MODULATOR & DELTA-SIGMA MODULATOR BASED SWITCHING POWER SUPPLY
AN ANALYSIS OF INTERLEAVER TYPES FOR BETTER BER PERFORMANCE IN LINEAR TURBO EQUALIZER
DESIGN OF SWITCHING POWER SUPPLY USING PWM MODULATOR & DELTA SIGMA MODULATOR
VLSI ARCHITECTURE OF ADAPTIVE CHANNEL EQUALIZER FOR MOBILE COMMUNICATION
A COMPARATIVE ANALYSIS OF SISO ALGORITHMS FOR “TURBO-RECOGNITION
HIGH SPEED SOC WITH A DIGITAL FAST LOCKING PULSE WIDTH CONTROLLER BASED CLOCK GENERATION
REDUCTION IN ERROR PROPGATION BY ELIMINATION IN DECISION-FEEDBACK EQUALIZATION
AN ANALYSIS OF TURBO EQUALIZATION
DESIGN 802.16e INTERLEAVER FOR FPGA IMPLEMENTATION
A COMPARATIVE ANALYSIS OF SISO ALGORITHMS FOR “TURBO-RECOGNITION
ADDRESS
Science Publishing Group
548 FASHION AVENUE
NEW YORK, NY 10018
U.S.A.
Tel: (001)347-688-8931