Cost Effective Method to Locate the Vulnerable Nodes of Circuits Against the Electrical Fast Transients
Journal of Electrical and Electronic Engineering
Volume 3, Issue 2-1, March 2015, Pages: 72-77
Received: Jan. 16, 2015; Accepted: Jan. 19, 2015; Published: Feb. 10, 2015
Views 2910      Downloads 189
Authors
Behnam Gholamrezazadeh Family, Communication Department, Niroo Research Institute, Tehran, Iran
Vahid Hamiyaty Vaghef, Communication Department, Niroo Research Institute, Tehran, Iran
Maryam Shabro, Communication Department, Niroo Research Institute, Tehran, Iran
Article Tools
Follow on us
Abstract
Electrical Fast Transients (EFT) pulses may cause a large number of circuits to fail. Switching power supplies, inductors, contact relays, and high voltage switches electrically or electromagnetically strike the data, address and control lines of processors, memory elements, or even analog parts and leads to soft or permanent errors. In general, compliant test is accomplished to address the susceptibility of circuits to EFT pulses. However, extremely high cost of these tests encounters the compliant test with difficulty. As a result, in this paper a low-cost EFT simulator circuit is proposed to locate the vulnerable parts of the circuit. The approach is easily applicable to any point of any circuit. The design is performed such that the proposed circuit does not damage the Equipment Under Test (EUT). Experimental results show that the proposed approach effectively detects the vulnerable circuits and practically has been used at the design phase of the DTPS-8C device.
Keywords
Electromagnetic Compatibility, EFT/B, Switching, Protection Devices
To cite this article
Behnam Gholamrezazadeh Family, Vahid Hamiyaty Vaghef, Maryam Shabro, Cost Effective Method to Locate the Vulnerable Nodes of Circuits Against the Electrical Fast Transients, Journal of Electrical and Electronic Engineering. Special Issue: Research and Practices in Electrical and Electronic Engineering in Developing Countries. Vol. 3, No. 2-1, 2015, pp. 72-77. doi: 10.11648/j.jeee.s.2015030201.26
References
[1]
IEC61000-4-4, "Electromagnetic compatibility (EMC), Part 4-4: Testing & measurement techniques – Electrical fast transient/ Burst immunity test", edition 3.0, 2012.
[2]
J. R. Barnes, "Designing Electronic Systems for ESD Immunity", Conformity magazine, Feb. 2003. Online at: http://www.dbicorporation.com/esd-art3.pdf.
[3]
S. Hyung, J. Young, "Analysis of Coupling Mechanism and Solution for EFT Noise on Semiconductor Device Level", Proceedings of the International Conference on Electromagnetic Interference and Compatibility, New Delhi, India, 6-8 Dec. 1999.
[4]
E. Rogers, "Understanding Boost Power Stages in Switch mode Power Supplies", Application Report, Mixed Signal Products, TI Literature Number SLVA061, 1999. Online at: http://www.ti.com/lit/an/slva061/slva061.pdf.
[5]
A. Tamuri, "Nanoseconds Switching for High Voltage Circuit Using Avalanche Transistors", Applied physics research, Vol. 1, No. 2, 2009. Online at: http://www.ccsenet.org/journal/index.php/apr/article/viewFile/3287/3601.
[6]
B. Gh. Family, V. H. Vaghef, and M. Shabro, "A Method for Determining the Critical Parts of Electronic Circuits into EFT/B", 7thSASTech international conference, Bandar-Abbas, Iran, 2013.
ADDRESS
Science Publishing Group
1 Rockefeller Plaza,
10th and 11th Floors,
New York, NY 10020
U.S.A.
Tel: (001)347-983-5186