Embedded Software Optimization for Computation - Intensive Applications
Journal of Electrical and Electronic Engineering
Volume 8, Issue 2, April 2020, Pages: 42-46
Received: Apr. 20, 2020; Accepted: May 9, 2020; Published: May 27, 2020
Views 63      Downloads 46
Amitkumar Mistry, Object Video Labs, McLean, USA
Rahul Kher, Department of Electronics & Communication Engg, G H Patel College of Engg & Tech, Vallabh Vidyanagar, India
Article Tools
Follow on us
Optimization metrics for compiled code are not always measured in execution clock cycles on the target architecture. Modern cellular telephone or wireless devices, which may download executables over a wireless network connection or backhaul infrastructure, it is often advantageous for the compiler to reduce the size of the compiled code that must be downloaded to the wireless device. By reducing the size of the code, savings are achieved in terms of bandwidth required for each wireless point of download. These are metrics correlated to the dynamic run-time behaviour of not only the compiled code on the target processor, but also the underlying memory system, caches, DRAM, and buses, etc. Despite new generation of embedded systems are getting innovative and computationally powerful with upcoming embedded processors, the market demands more computational-intensive embedded software to be developed on embedded systems. It is very essential to implement efficient embedded software to meet the market demand of embedded systems. These embedded systems are special-purpose computing systems and built to perform very specific embedded applications. And, these embedded applications mainly use three key resources of embedded systems: (1) CPU (2) Run-time memory (3) Persistent memory i.e. NAND/NOR flash memory. This paper summarizes several effective embedded software optimization techniques to optimize CPU usage, Run-time memory, and Persistent memory.
System-on-Chip (SoC), CPU, Run-Time Memory, Persistent Memory, Optimization Techniques
To cite this article
Amitkumar Mistry, Rahul Kher, Embedded Software Optimization for Computation - Intensive Applications, Journal of Electrical and Electronic Engineering. Special Issue: Soft Computing Methods for Electrical and Electronics Engineering Applications. Vol. 8, No. 2, 2020, pp. 42-46. doi: 10.11648/j.jeee.20200802.11
Copyright © 2020 Authors retain the copyright of this article.
This article is an open access article distributed under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/4.0/) which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
P. R. Panda, F. Catthoor, N. D. Dutt, K. Danckaert, E. Brockmeyer, C. Kulkarni, A. Vandercappelle, and P. G. Kjeldsberg, “Data and memory optimization techniques for embedded systems,” ACM Transactions on Design Automation of Electronic Systems (TODAES) April 2001.
Christian Zinner, Wilfried Kubinger, “A DMA Double Buffering Method for Embedded Image Processing with Resource Optimized Slicing”, RTAS 2006.
Bellas, N., Hajj, I. N., Polychronopoulos, C. D., and Stamoulis, G. 2000. Architectural and compiler techniques for energy reduction in high-performance microprocessors. IEEE Trans. Very Large Scale Integr. Syst. 8, 3 (June), 317–326.
Danckaert, K., Catthoor, F., and Man, H. D. 2000. A preprocessing step for global loop transformations for data transfer and storage optimization. Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems, San Jose, USA.
Fraboulet, A., Huard, G., and Mignotte, A. 1999. Loop alignment for memory access optimisation. In Proceedings of the 12th ACM/IEEE International Symposium on System- Level Synthesis (San Jose CA, Dec.). ACM Press, New York, NY, 70–71.
Kirovski, D., Lee, C., Potkonjak, M., and Mangione-Smith, W. 1999. Application-driven synthesis of memory-intensive systems-on-chip. IEEE Trans. Computer-Aided Des. 18, 9 (Sept.), 1316–1326.
Masselos, K., Catthoor, F., Goutis, C. E., and Man, H. D. 1999. A performance-oriented use methodology of power optimizing code transformations for multimedia applications realized on programmable multimedia processors. In Proceedings of the IEEE Workshop on Signal Processing Systems (Taipeh, Taiwan). IEEE Computer Society Press, Los Alamitos, CA, 261–270.
Panda, P. R., Dutt, N. D., and Nicolau, A. 2000. On-chip vs. off-chip memory: The data partitioning problem in embedded processor-based systems. ACM Trans. Des. Autom. Electron. Syst. 5, 3 (July), 682–704.
Shiue, W. and Chakrabarti, C. 1999. Memory exploration for low power, embedded systems. In Proceedings of the 36th ACM/IEEE Conference on Design Automation (New Orleans LA, June). ACM Press, New York, NY, 140–145.
Shiue, W.-T., Tadas, S., and Chakrabarti, C. 2000. Low power multi-module, multi-port memory design for embedded systems. In Proceedings of the IEEE Workshop on Signal Processing Systems (Lafayette, LA, Oct.). IEEE Press, Piscataway, NJ, 529–538.
Eric S. Raymon, “The Lost Art of Structure Packing,” http://www.catb.org/esr/structure-packing/.
Kevin Kredit, “Write Vectorized Code and Optimize Your CPU Performance”, https:// dornerworks.com/ blog/ write- vectorized-code-and-optimize- your-cpu- performance/.
Yemliha, Taylan, "Performance and Memory Space Optimizations for Embedded Systems" (2011). Electrical Engineering and Computer Science - Dissertations. 300. https://surface.syr.edu/eecs_etd/300
Editor’s note. https://www.embedded.com/ achieving- better- software-performance-through-memory-oriented-code-optimization-part-1/
Ph. D Thesis. Design and Optimization of Architectures for Data Intensive Computing, available at http://users.ece.northwestern.edu/~jay/PhD_Dissertation.pdf
E. H. M. Sha, "Parallel embedded systems: optimizations and challenges," IEEE Int. Conf. on Emerging Information Technology, Taipei, 2005, pp. 4-9.
Science Publishing Group
1 Rockefeller Plaza,
10th and 11th Floors,
New York, NY 10020
Tel: (001)347-983-5186