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Survey of Low Power Testing of VLSI Circuits
Science Journal of Circuits, Systems and Signal Processing
Volume 2, Issue 2, April 2013, Pages: 67-74
Received: Apr. 13, 2013; Published: May 20, 2013
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P. Basker, Department Of Ece, Kongu Engineering College, Perundurai, Tamil Nadu, India
A. Arulmurugan, Department Of Ece, Kongu Engineering College, Perundurai, Tamil Nadu, India
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The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, reduced autonomy of portable systems, and decrease of overall yield. This paper surveys about the available low power testing techniques during testing. It also suggests some advantages and disadvantages associated with every techniques
Dft, Bist, Lfsr, Cut, Atpg
To cite this article
P. Basker, A. Arulmurugan, Survey of Low Power Testing of VLSI Circuits, Science Journal of Circuits, Systems and Signal Processing. Vol. 2, No. 2, 2013, pp. 67-74. doi: 10.11648/j.cssp.20130202.15
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