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Hardware Simulator for MIMO Propagation Channels: Time Domain Versus Frequency Domain Architectures
Science Journal of Circuits, Systems and Signal Processing
Volume 2, Issue 2, April 2013, Pages: 37-55
Received: Apr. 23, 2013; Published: Apr. 2, 2013
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Bachir Habib, Institute of Electronics and Telecommunications of Rennes, IETR, UMR CNRS 6164, Rennes, France
Gheorghe Zaharia, Institute of Electronics and Telecommunications of Rennes, IETR, UMR CNRS 6164, Rennes, France
Ghais El Zein, Institute of Electronics and Telecommunications of Rennes, IETR, UMR CNRS 6164, Rennes, France
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A hardware simulator facilitates the test and validation cycles by replicating channel artifacts in a controllable and repeatable laboratory environment. This paper presents an overview of the digital block architectures of Multiple-Input Multiple-Output (MIMO) hardware simulators. First, the simple frequency architecture is presented and analyzed. Then, an improved frequency architecture, which works for streaming mode input signals, is considered. After, the time domain architecture is described and analyzed. The architectures of the digital block are presented and designed on a Xilinx Virtex-IV Field Programmable Gate Array (FPGA). Their accuracy, occupation on the FPGA and latencies are analyzed using Wireless Local Area Networks (WLAN) 802.11ac and Long Term Evolution System (LTE) signals. The frequency and the time approaches are compared and discussed, for indoor (using TGn channel models) and outdoor (using 3GPP-LTE channel models) environments. It is shown that the time domain architecture present the best solution for the design of the architecture of the hardware simulator digital block. Finally, a 2×2 MIMO time domain architecture is described and simulated with input signal that respects the bandwidth of the considered standards.
Hardware Simulator, MIMO Radio Channel, FPGA, 802.11ac, LTE
To cite this article
Bachir Habib, Gheorghe Zaharia, Ghais El Zein, Hardware Simulator for MIMO Propagation Channels: Time Domain Versus Frequency Domain Architectures, Science Journal of Circuits, Systems and Signal Processing. Vol. 2, No. 2, 2013, pp. 37-55. doi: 10.11648/j.cssp.20130202.13
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