Context Adaptive Variable Length Decoding Optimization and Implementation on Tms320c64 Dsp for H.264/Avc
Science Journal of Circuits, Systems and Signal Processing
Volume 2, Issue 1, February 2013, Pages: 6-15
Received: Feb. 22, 2013; Published: Feb. 20, 2013
Views 3017      Downloads 132
Authors
Taheni Damak, Higher Institute of Computer Sciences and Communication Technologies of Hamam Sousse, University of Sousse, Sousse, Tunisia
Imen Werda, Higher Institute of Applied Sciences and Technology, University of Sousse, Sousse, Tunisia
Mohamed Ali Ben Ayed, Higher Institute of Electronics and Communication of Sfax, University of Sfax, Sfax, Tunisia
Nouri Masmoudi, National School of Engineers of Sfax, University of Sfax, Sfax, Tunisia
Article Tools
PDF
Follow on us
Abstract
Context Adaptive Variable Length Decoding (CAVLD) module takes the lion chair of the H.264/AVC video decoder time due to its complexity. In order to ameliorate decoding speed, a new CAVLD algorithm and an efficient internal memory design were implemented on Digital Signal Processor (DSP). The proposed CAVLD algorithm, Zero Length Prefix (ZLP), was designed to optimize the first syntax element: the CoeffToken. ZLP implementation reduces CAVLD execution time to 21% instead of 41% from decoding time with a throughput of 1.28 MegaMB/s. In addition, the decoder speed was increased from 36 frames per second (fps) to 44 fps for a CIF compressed bitstream.
Keywords
H.264 Video Coding Standard, Decoder, CAVLD, Coefftoken, TMS320C64 DSP
To cite this article
Taheni Damak, Imen Werda, Mohamed Ali Ben Ayed, Nouri Masmoudi, Context Adaptive Variable Length Decoding Optimization and Implementation on Tms320c64 Dsp for H.264/Avc, Science Journal of Circuits, Systems and Signal Processing. Vol. 2, No. 1, 2013, pp. 6-15. doi: 10.11648/j.cssp.20130201.12
References
[1]
Joint Video Team (JVT) of ITU-T VCEG and ISO/IEC MPEG, "Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification", ITU-T Rec. H.264 and ISO/IEC 14496-10 AVC, May 2003.
[2]
Yong Ho Moon, Gyu Yeong Kim, and Jae Ho Kim, "An Efficient Decoding of CAVLC in H.264/AVC Video Coding Standard", Transactions on Consumer Electronics, Volume: 51 , Issue: 3, pp 933 – 938, 2005.
[3]
Jari Nikara, Stamatis Vassiliadis, Jarmo Takala, Mihai Sima, and Petri Liuha, "Parallel Multiple-Symbol Variable-Length Decoding". International Conference on Computer Design. Freiburg, Germany. ICCD 2002.
[4]
MythriAlle,JBiswas,S.K.Nandy "High Performance VLSI Architecture Design for H.264 CAVLC Decoder", Application-Specific Systems, Architecture and Processors. Colorado, USA. ASAP 2006.
[5]
Hsiu-Cheng Chang, Chien-Chang Lin, and Jiun-In Guo, "A Novel Low-Cost High-Performance VLSI Architecture for MPEG-4 AVC/H.264 CAVLC Decoding", Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on, volume 6, pp 6110 - 6113, May 2005.
[6]
Myungseok Oh, Wonjae Lee, Yunho Jung, and Jaeseok Kim, "Design of High-Speed CAVLC Decoder Architecture for H.264/AVC". ETRI 2008 Journal, Volume 30, Number 1, February 2008.
[7]
Yuan-Hsin Liao, Gwo-Long Li, and Tian-Sheuan Chang, "A 385MHz 13.54K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video ", IEEE transactions on circuits and systems for video technology, volume 22, no. 11, pp 1604-1610. , November 2012.
[8]
Tony Gladvin George, Dr.N.Malmurugan, "A New Fast Architecture for HD H.264 CAVLC multi-syn Decoder and its FPGA Implementation". International Conference on Computational Intelligence and Multimedia Applications. Sivakasi, India. ICCIMA 2007.
[9]
Tsung-Han Tsai, Member, IEEE, Te-Lung Fang, and Yu-Nan Pan, "A Novel Design of CAVLC Decoder with Low Power and High Throughput Considerations", IEEE transactions on circuits and systems for video technology, volume 21, no. 3, pp 311-319, March 2011.
[10]
Shau-Yin Tseng, Tien-Wei Hsieh, "A Pattern-Search Method for H.264/AVC CAVLC decoding", Multimedia and Expo, 2006 IEEE International Conference on, pp 1073 – 1076, Jully 2006.
[11]
Iain E.G. Richardson, "H.264 and MPEG-4 Video Compression – video coding for next generation multimedia". John Wiley & Sons, pp.187-207. 2003.
[12]
Taheni Damak, Imen Werda, Sébastien Bilavarn, Nouri Masmoudi, "Fast prototyping H.264 deblocking filter using ESL tools", 8th International Multi-Conference on Systems, Signals & Devices. Tunisia. SSD 2011.
[13]
Texas Instuments, 2001.TMS320 C¬64x Technital overview. spru395b, Janvier 2001.
[14]
I. Werda, H. Chaouch, A. Samet, M.A. Ben Ayed and N. Masmoudi, "Optimal DSP-Based Motion Estimation Tools Implementation For H.264/AVC Baseline Encoder". International Journal of Computer Science and Network Security, IJCSNS, VOL.7 No.5, May 2007.
[15]
T.Damak, I.Werda, A.Samet, N.Masmoudi, "DSP CAVLC implementation and Optimization for H.264/AVC baseline encoder", IEEE International Conference on Electronics, Circuits and Systems. Malte. ICESC, 2008.
[16]
Werda. I, Dammak. T, Grandpierre. T, Ben Ayed MA, Masmoudi N, " Real-time H.264/AVC baseline decoder implementation on TMS320C6416", Springer-Verlag 2010, J Real-Time Image Processing, Volume 7, Issue 4, pp 215-232.
[17]
Damak T., Werda I., Ben Ayad M-A, Masmoudi N, "An Efficient Zero Length Prefix Algorithm for H.264 CAVLC Decoder on TMS320C64", International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS). Tunisia, 2010.
[18]
Yanmei Qu, Yun He and Shunliang Mei, "A Novel Cost-Effective and Programmable VLSI Architecture of CAVLC Decoder for H.264/AVC". Journal of Signal Processing Systems, Springer Science + Business Media, LLC. Volume 50, pp 41- 51 , 2008.
[19]
Klaus Schoffmann, Markus Fauster, Oliver Lampl, and Laszlo Bosz ormenyi , " An Evaluation of Parallelization Concepts for Baseline-Profile Compliant H.264/AVC Decoders". LNCS 4641, pp. 782–791, 2007. Springer-Verlag Berlin Heidelberg. 2007.
[20]
Sangyoon Park, Kyeongyuk Min, Jongwha Chong, "The New Memory-Efficient Hardware Architecture of CAVLD in H.264/AVC for Mobile System", Communications and Information Technology, 2009. 9th International Symposium on, pp 204-207. ISCIT 2009.
ADDRESS
Science Publishing Group
1 Rockefeller Plaza,
10th and 11th Floors,
New York, NY 10020
U.S.A.
Tel: (001)347-983-5186